Architectural Simulation to Accelerate CoDesign
The architectural simulation of computing systems plays an essential role in providing performance and power predictive capability because it enables the rapid quantitative exploration of HPC system design tradeoffs. Three tools which work synergistically together to provide a complete codesign simulation tool set are the ROSE compiler, the ACE emulation platform, and the SST simulator.
The SST simulator consists of two tools: SST/macro and SST/micro. SST/macro is a coarse-grained simulator which lets designers study large-scale systems in a way that captures the complex interactions among hardware components. SST/macro can use a skeleton application that domain experts provide or ROSE-based analysis tools generate which scales and behaves exactly like the original application code, enabling investigating the communication characteristics and bottlenecks of applications that may arise only at the scales which are predicted for next-generation machines. Designers can also replay traces of a previously run MPI application through the simulator, allowing its execution time to be estimated on new hardware or validating the simulator against existing hardware. SST/micro is a general simulation framework which can be used to compose complete simulations of HPC compute nodes by combining cycle-accurate models of processors, memory, disks, and network routers to explore detailed node-level architectural design tradeoffs in both hardware and software.
For more information, please contact John Shalf of Lawrence Berkeley National Laboratory at firstname.lastname@example.org.